Finfet Technology Seminar report







FinFET technology processing on SOI wafers uses standard manufacturing process modules. To etch the ultra thin (T SI =15nm) fins, spacer lithography [side wall image transfer] is used. Since the SIT process always generates an even number of fins, an extra process step is needed for removal of fins to allow odd number of fins or otherwise break fin" "loops" where needed. This means, that for conversion of an existing design, two additional levels have to be introduced, namely the " fin" and the "Trim" level. All other design levels remain the same. Consider now a planar design to be converted for processing in the 90 nm FinFET technology node. The FinFET height H Fin together with the fin pitch (determined by photolithography) defines the FinFET device width W Fin within the given silicon width of the planar device, to get the same or better device strength . For automatic Fin and Trim generation, Fin-GEN, a software tool, has been developed, which takes the active area and poly gate levels, and, based on special FinFET ground rules, generates the additional levels.the circuit (as well as other β-ratio sensitive circuitry) may additionally require manual adjustment on the number of fins in the N- and P-devices after automatic addition of fins in the N- and P- devices after automatic addition of the FinFET levels. Besides device width quantization, other factors like width variation, threshold variation, and self- heating must be taken into account when designing with FinFETs. A process with multiple threshold voltages and multiple gate oxide thickness is required to take full advantage of this new device. As already discussed, the width quantization imposes some restrictions on the device strength flexibility, but most of them can be absorbed easily when converting an existing design or starting a new design, respectively. Of course, as stated earlier, latches, dynamic circuit styles in general, and SRAM cells need careful optimization when designing with FinFETs.






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